Improving Application Performance by Dynamically Trading Frequency for Complexity in a GALS Microprocessor∗

Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by “downsizing” hardware resources that are underutilized by the current application. We explore the converse: improving performance by “upsizing” resources for which the application has greater needs. Our proposal depends critically on the ability to change frequencies independently in separate domains of a globally asynchronous, locally synchronous (GALS) microprocessor. We use a variant of a multiple clock domain (MCD) processor, with four independently clocked domains. Each domain is streamlined with modest hardware structures for very high clock frequency. Key structures can then be upsized on demand to exploit more distant parallelism, improve branch prediction, or increase cache capacity. Although doing so requires decreasing the associated domain frequency, other domain frequencies are unaffected. Measuring across a broad suite of application benchmarks, we find that configuring our MCD processor just once per application yields performance 17.6% better, on average, than that of the “best overall” fully synchronous design. By adapting automatically to application phases, we can increase this advantage to more than 20%. ∗This work was supported in part by NSF grants CCR-9701915, CCR-9811929, CCR-9988361, EIA-0080124, and CCR-0204344; by DARPA/ITO under AFRL contract F29601-00-K-0182; by and IBM Faculty Partnership Award; and by equipment grants from IBM and Intel. Authors’ current addresses: Greg Semeraro, Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY 14623, [email protected]; David Albonesi, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, [email protected]; Steven Dropsho, EPFL–IC–LABOS, CH 1015 Lausanne, Switzerland, [email protected]; Grigorios Magklis, Intel Labs Barcelona, Jordi Girona 29-3A, 08034 Barcelona, Spain, [email protected]; Michael Scott, Department of Computer Science, University of Rochester, Rochester, NY 14627, [email protected].